1. Field of the Invention
This invention relates generally to DRAM memories and relates more particularly to driving circuits of local word line drivers of DRAMs.
2. Description of the Prior Art
The optimization of the energy consumption of memory systems gets more and more important. Many modern computer applications are data-intensive and nowadays for ASICs and embedded systems the memory components contribute up to 90% of the energy consumption of the data processing system.
DRAM circuit designs require often that bit lines require power supply voltage level VDD while word-line drivers have to provide an output voltage VPP that has to be above the VDD voltage level. This is achieved by boosting the supply (VDD) voltage level to a higher voltage than the voltage of the cell capacitor. The high level of VPP is necessary for DRAM array operation, but at the expense of a higher current consumption due to decreased pumping efficiency while VDD becoming lower.
There are various known patents dealing with the optimization of energy consumption of memory systems:
U.S. Pat. No. (6,236,617 to Hsu et al.) teaches a negative word-line DRAM array having n groups of m word-lines, in which one group is driven by a group decoder circuit (having a voltage swing between ground and a circuit high voltage (2 v)) and one driver circuit in each group is exposed to a boosted word-line high voltage (2.8 v) greater than the circuit high voltage, in which the word-line driver circuits have an output stage comprising a standard nfet in series with a high threshold voltage pfet, so that, during activation, the unselected driver circuits exposed to the boosted word-line high voltage have a very low leakage through the pfet, while the selected driver circuit has a high but tolerable leakage (2 .mu.A) because Vqs on the nfet is nearly at the nfet threshold. The net active power from the entire array is less than that of a conventional configuration due to the reduced voltage swing, while the number of transistors exposed to high voltage stress is reduced from 9 to 1 and the number of buffer nfets required to reduce voltage drop across an active nfet is reduced from 8 to 1.
U.S. Pat. No. (5,202,855 to Morton) discloses a DRAM containing both driver control logic and level shifting driver circuitry to generate a voltage boosted word-line signal. The driver control logic receives timing signals and row address information to provide timing control signals for the level-shifting driver. The level-shifting driver provides a voltage boosted word-line signal for a predetermined period of time in response to the timing control signals. Furthermore, the driver control logic provides control to the level shifting driver circuit to assure that transistors that drive the word-line signal are not damaged by voltage during a switching transition.
U.S. Pat. No. (6,747,904 to Chen) introduces a leakage control circuit and DRAM equipped therewith. The leakage control circuit includes a differential amplifier, a first voltage divider, a second voltage divider, MOS transistors, and a charge pump. The first voltage divider generates a first reference voltage. The second voltage divider generates a second reference voltage. The differential amplifier has a first input receiving the first reference voltage, a second input receiving the second reference voltage, and an output coupled to the input of the charge pump. MOS transistors have drains coupled to the first input of the differential amplifier, gates coupled to the output of the charge pump, and sources coupled to a ground potential.